Recent project had many problems due to long part searching and many dead ends. The main problem was 4-to-16 multiplexer and demultiplexer (actually I needed 4-to-9, because there are 9 devices), since 74HC154 is available, but SY100S364 is hard to get here and it does not support 3V3 levels, so I have decided to use Xilinx XC9572XL CPLD device in VQ44 package to make mux/demux device.
Firstly, I had to make a programmer to program CPLD. Xilinx offers JTAG device called Xilinx Paraller III and can be found HERE. Here how it looks like:
I have run out of 100ohm resistors, but 110ohm works fine, also 5k1 resistor can be replaced with 1k and the diode can be replaced with more common 1N4148. iMPACT should find the programmer after connecting it to LPT port.
Now it is time to test CPLD, so I have made a small development board for Xilinx XC9536(XL) and XC9572(XL) devices. Here is the schematic:
XC9572 and XC9536 development board
It is very simple and easy to make at home. My PCB etched at home looks like this:
Devboard PCB
And finally, the complete development board:
Devboard TOP
With this board it was easy to test my code, also it is easy to make other simple programs with CPLD, the only thing if You need is an external clock, but this is not a big problem since there are connectors left for an every pin of the CPLD.
Now the funniest part – the code. I prefer VHDL, so my code is written in VHDL also this code is for 4-to-9 mux/demux interface, but You can easily extend it using mux/demux tables from 74HC154 datasheet. The code is easy and the device does not need any clocks, since levels change is needed only on input change:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity vhdl is
Port ( Q : out STD_LOGIC_VECTOR (8 downto 0);
R : out STD_LOGIC_VECTOR (3 downto 0);
A : in STD_LOGIC;
B : in STD_LOGIC;
C : in STD_LOGIC;
D : in STD_LOGIC;
E : in STD_LOGIC;
F : in STD_LOGIC;
G : in STD_LOGIC;
H : in STD_LOGIC;
I : in STD_LOGIC;
J : in STD_LOGIC;
K : in STD_LOGIC;
L : in STD_LOGIC;
M : in STD_LOGIC);
end vhdl;
architecture decoder_arch of vhdl is
signal AIN_DATA : STD_LOGIC_VECTOR(3 downto 0);
signal BIN_DATA : STD_LOGIC_VECTOR(8 downto 0);
begin
AIN_DATA <= D & C & B & A;
BIN_DATA <= M & L & K & J & I & H & G & F & E;
process( AIN_DATA ) begin
case AIN_DATA is
when "0000" => Q <= "000000001";
when "0001" => Q <= "000000010";
when "0010" => Q <= "000000100";
when "0011" => Q <= "000001000";
when "0100" => Q <= "000010000";
when "0101" => Q <= "000100000";
when "0110" => Q <= "001000000";
when "0111" => Q <= "010000000";
when "1000" => Q <= "100000000";
when others => Q <= "000000001";
end case;
end process;
process( BIN_DATA ) begin
case BIN_DATA is
when "000000001" => R <= "0000";
when "000000010" => R <= "0001";
when "000000100" => R <= "0010";
when "000001000" => R <= "0011";
when "000010000" => R <= "0100";
when "000100000" => R <= "0101";
when "001000000" => R <= "0110";
when "010000000" => R <= "0111";
when "100000000" => R <= "1000";
when others => R <= "0000";
end case;
end process;
end decoder_arch;
Hope this helps somebody.
P.S. The code can contain BUGS!
References:
http://ad7gd.net/xc9536/
http://www.ulrichradig.de/home/index.php