Socrates lounge

Hello my readers, if I have any Summer is going on, my studies in FPGAs should also have an increase, but I had only a couple of days for vacation. Work work work! However I will keep my post short. This time I have implemented LTC2624 Quad 12bit DAC, which is placed on my Spartan-3E devkit, in VHDL. The module could be a bit tidier, but I think it is very easy to understand, plus I added some comments in the source. However, I am still bad in testbenches, so if someone would like to do it – contact me or leave a post . Anyway, this design is FPGA proven, so You can freely use it. Here are the photos (the value is set to decimal 2048):
Channels A and B:

Channels C and D:

Refer to Spartan-3E board datasheet and LTC2624 datasheet for exact voltage calculation.
The design works in 32bit mode, which I found in S3E board datasheet, however later I’ve checked the DAC datasheet and it still works in 24bit mode, so if You need more speed – remove unused 8 bits and use this in 24bit mode.

P.S. If there is anyone, who could write a testbench, we could both add this project to OpenCores, because testbench is a requirement there afaik.

The IP is available HERE.